Voltage controlled oscillator using capacitive degeneration

ABSTRACT

A VCO is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties of the disclosed VCO combined with small effective capacitance enable low-power low-noise high-frequency VCO implementations.

RELATED APPLICATION

This application claims priority under 35 U.S.C. 119(e) from U.S.Provisional Application Ser. No. 60/650,489 filed Feb. 7, 2005, whichapplication is incorporated herein by reference.

LIMITED COPYRIGHT WAIVER

A portion of the disclosure of this patent document contains material towhich the claim of copyright protection is made. The copyright owner hasno objection to the facsimile reproduction by any person of the patentdocument or the patent disclosure, as it appears in the U.S. Patent andTrademark Office file or records, but reserves all other rightswhatsoever. Copyright © 2005, Regents of the University of Minnesota.

FIELD

The embodiments relate generally to voltage controlled oscillators andmore particularly to a voltage controlled oscillator using capacitivedegeneration.

BACKGROUND

Today there are a wide variety of computer and telecommunicationsdevices, such as personal computers (PCs), mobile telephones, andpersonal digital assistants (PDAs), that need to share information witheach other. Generally, this information is communicated from a sendingdevice to a receiving device.

The sending device generally has the data in the initial form of a setof digital words (sets of ones and zeros). In the sending device, atransmitter circuit converts each word into a sequence of electricalpulses, and transmits the sequence of pulses through a cable, circuitboard, or other medium to the receiving device. The receiving deviceincludes a receiver circuit that identifies each of the pulses in thesignal as a one or zero, enabling it to reconstruct the original digitalwords.

A key component in both the transmitter and the receiver is avoltage-controlled oscillator, a circuit that produces a signal thatvaries back and forth between two voltage levels at a frequency based onan input control voltage. The transmitter uses a VCO to place digitalinformation into a high-frequency carrier signal, and the receiver usesa VCO to separate the digital information from the high-frequencycarrier signal. Thus, voltage-controlled oscillators (VCOs) are criticalbuilding blocks in high-performance communication systems. Theever-increasing demand for bandwidth places very stringent frequency,power, and noise requirements on such systems.

SUMMARY

In general, the embodiments of the invention are directed to a voltagecontrolled oscillator (VCO) design using capacitive degeneration. TheVCO employs a negative resistance cell topology that supportshigh-frequency performance in a low-power, low-noise implementation.

The VCO may include a negative resistance cell that is based on acapacitively emitter-degenerated topology, but employs a cross-coupledMOS pair as a degeneration cell. The cross-coupled MOS pair contributesadditional conductance and allows the negative resistance cell to have ahigher maximum attainable oscillation frequency and enhanced negativeresistance characteristics in comparison with other topologies at highfrequencies. These properties, combined with relatively small effectivecapacitance, enable low-power, low-noise high-frequency VCOimplementations.

In one embodiment, a negative resistance cell is formed by two bipolartransistors that are interconnected via two field-effect transistors,such as NMOS field-effect transistors. An emitter of a first bipolartransistor is coupled to a gate of a first field-effect transistor and adrain of a second field-effect transistor. An emitter of a secondbipolar transistor is coupled to a gate of the second field-effecttransistor and a drain of the first field-effect transistors. In thismanner, the two bipolar transistors are interconnected using thecross-coupled field-effect transistor pair.

The capacitance between the gate and the source of each of thefield-effect transistors provides a capacitance that is equivalent to adegeneration capacitor of a capacitive emitter degenerated transistor.In addition, the positive feedback path of the cross-coupledfield-effect transistors provides additional transconductance to improvethe negative resistance value. The combined effect of the emitterdegeneration and the additional transconductance allow the negativeresistance cell to generate an effective negative resistance using smallbias currents, thus reducing power consumption and noise contribution ofthe VCO core.

The VCO also may include a current source that: is connected to thesource of each of the field-effect transistors. Additionally, the VCOmay include one or more buffers to buffer the output of the VCO. In oneembodiment, the VCO includes a pair of buffers, one coupled to theemitter of the first bipolar transistor and the other coupled to theemitter of the second bipolar transistor, An exemplary buffer foreffectively buffering the output of the VCO is an emitter-follower.

Some embodiments may provide various advantages over simplecross-coupled negative resistance cells and capacitoremitter-degenerated negative resistance cells. For example, the combinedeffect of the emitter degeneration and the additional transconductanceallows the negative resistance cell to generate an effective negativeresistance using small bias currents, thus reducing power consumptionand noise contribution of the VCO core. In addition, the cross-coupledfield-effect transistors increase the maximum attainable oscillationfrequency of the VCO. Also, in some embodiments the common-modeadmittance of the field-effect transistor pair is near zero reducing thesusceptibility of the VCO to common-mode oscillations.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments are illustrated by way of example and not limitation in thefigures of the accompanying drawings, in which like references indicatesimilar elements and in which:

FIG. 1 is an illustration of a parallel LC oscillator circuit model.

FIGS. 2A-2D illustrate cross-coupled negative resistance cells.

FIGS. 3A and 3B are graphs illustrating the negative resistance for across-coupled cell.

FIG. 4 is circuit schematic for a VCO core coupled to a buffer.

FIG. 5 illustrates a parallel LC oscillator model including buffer stageimpedance.

FIGS. 6A and 6B are oscillator output admittance examples for BJT andMOS VCOs.

FIG. 7 illustrates pole frequency versus load capacitance of the bufferstage.

FIG. 8 illustrates a single-ended negative resistance cell usingcapacitive emitter degeneration.

FIG. 9 illustrates a differential negative resistance cell usingcapacitive degeneration and cross-coupled MOS transistors according toembodiments of the invention.

FIG. 10 illustrates an equivalent small-signal circuit model for thenegative resistance cell illustrated in FIG. 9 according to embodimentsof the invention.

FIG. 11 is a plot of R versus δ for different values of g_(m1).

FIG. 12 is a plot of simulated R_(Eq) for the cross-coupled,capacitively degenerated, and cells according to embodiments of theinvention.

FIG. 13 is a plot of simulated R_(Eq) for the cross-coupled,capacitively degenerated, and cells according to embodiments of theinvention.

FIG. 14 illustrates a common-mode circuit equivalent for a capacitivelyemitter-degenerated cell according to embodiments of the invention.

FIG. 15 is a plot showing common-mode negative resistance simulationresults.

FIG. 16 illustrates a common-mode tank schematic with bias networkimpedance according to embodiments of the invention.

FIG. 17 is a graph illustrating common-mode and differential-modeoscillation simulations.

FIGS. 18A and 18B illustrate tank-loading characteristics of across-coupled cell and a cell according to embodiments of the invention.

FIG. 19 is a graph illustrating a simulated tuning range versuseffective capacitance of a negative resistance cell according toembodiments of the invention.

FIG. 20 is a chip microphotograph and layout according to embodiments ofthe invention.

FIG. 21 shows the measured output power spectrum of a 20-GHz oscillationsignal according to an embodiment of the invention.

FIGS. 22A and 22B are graphs illustrating measured tuning range andsimulated frequency variation according to the temperature and processvariation and according to an embodiment of the invention.

FIG. 23 is a graph illustrating measured power variation in anembodiment of the invention.

FIGS. 24A and 24B illustrate phase-noise measurement of an embodiment ofthe invention.

FIG. 25 is a graph illustrating locking range and phase-noisemeasurement results of an embodiment of the invention.

DETAILED DESCRIPTION

In the following detailed description of example embodiments, referenceis made to the accompanying drawings which form a part hereof, and inwhich is shown by way of illustration specific embodiments in which theexample method, apparatus and system may be practiced. It is to beunderstood that other embodiments may be utilized and structural changesmay be made without departing from the scope of this description.

In the following detailed description, reference is made to specificexamples by way of drawings and illustrations. These examples aredescribed in sufficient detail to enable those skilled in the art topractice the inventive subject matter, and serve to illustrate how theinventive subject matter may be applied to various purposes orembodiments. Other embodiments are included within the inventive subjectmatter, as logical, mechanical, electrical, and other changes may bemade to the example embodiments described herein. Features orlimitations of various embodiments described herein, however essentialto the example embodiments in which they are incorporated, do not limitthe inventive subject matter as a whole, and any reference to theinvention, its elements, operation, and application are not limiting asa whole, but serve only to define these example embodiments. Thefollowing detailed description does not, therefore, limit embodiments ofthe invention, which are defined only by the appended claims.

I. LC-Tank-Based VCO Design Factors

This section analyzes the maximum attainable frequency of oscillation ofa typical LC VCO which uses the traditional cross-coupled negativeresistance cell. In addition, differences in behavior of a BJT-based anda CMOS-based negative resistance cell are discussed. A novel negativeresistance cell that overcomes the frequency limits of the traditionalcross-coupled negative resistance cell is presented along with designissues related to the novel architecture.

FIG. 1 shows a simplified circuit model for a parallel LC oscillator insteady state, where the resistance R_(p) represents the tank loss,R_(Eq) is the effective negative resistance generated by the activedevices, and C_(Eq) is the effective shunt capacitance contributed bythe active devices in the negative resistance cell. For stableoscillation, the magnitude of the effective negative resistance R_(Eq)has to be smaller than R_(p). Additionally, for high-frequency operationwhere C_(Var) is small, the effective capacitance C_(Eq) becomescomparable to C_(Var) and may significantly limit the maximum attainableoscillation frequency and tuning range.

The traditional cross-coupled cell which is known also as the negativeg_(m) cell is used widely due to its simplicity and its ability fordifferential signaling. First, limitations of the traditionalcross-coupled cell in both BiCMOS and CMOS form are discussed. Thoughsome embodiments are implemented in the IBM SiGe BiCMOS process, forcomparison purposes, all simulations discussed in this specification useeither the 0.25-m IBM SiGe BiCMOS process or the 0.18-mTSMC CMOSprocess.

In some parts of this section, small-signal models are used for thebehavioral analysis of the different negative resistance cells.

A. Maximum Attainable Oscillation Frequency for the Cross-CoupledNegative Resistance Cell

This section evaluates the maximum frequency of oscillation for a givenpower budget for BJT and MOS implementations of the cross-coupledstructure. Several factors (e.g., negative resistance cell design,buffer stage bandwidth, frequency tuning range, and the parasiticcapacitances of the constituent components) affect the maximumoscillation frequency. Due to its higher transconductance per unitcurrent, the BJT implementation provides a better R_(Eq). However, aswill be shown later, the finite base resistance severely limits themaximum attainable oscillation frequency.

1) Negative Resistance Cell

Mechanisms that degrade high-frequency performance in a cross-couplednegative resistance cell will now be considered. FIGS. 2A-2D showsimplified circuit schematics for the BJT-based (FIG. 2A) and CMOS-based(FIG. 2B) cross-coupled cells, the shunt equivalent model (FIG. 2C), andthe differential small-signal R_(Eq ∥)C_(Eq) model for the BJT version(FIG. 2D). At low frequencies, R_(Eq) is approximately −2/g_(m) whereg_(m) is the device transconductance. Typically, BJTs have a higherg_(m) than CMOS transistors for a given bias current and may be a betterchoice for low-power design. Additionally, the lower flicker noisecorner may make BJT devices a better candidate for low-power low-noiseoscillator design. However, with increasing frequency, the magnitude of|R_(Eq)| becomes large and eventually R_(Eq) flips over and becomespositive. This is primarily due to the non-negligible base resistance,r_(b), at high frequencies.

At high frequencies, the impedance offered by the base-emittercapacitance C_(π) becomes comparable to r_(b) with a result that alarger portion of the base voltage will appear across r_(b) rather thanC_(π). Additionally, there is a phase difference between the voltageacross C_(π) and the base voltage due to the resistor-capacitor voltagedivision. The voltage across C_(π) can be calculated using thesmall-signal model shown in FIG. 2D. Using the voltage division ratiov_(π)/v_(in), an effective transconductance may be defined as:

$\begin{matrix}{G_{m,{eff}} \equiv \frac{v_{\pi}}{v_{i\; n}} \equiv {A\;{\mathcal{g}}_{m}}} & (1)\end{matrix}$In FIG. 2D, the difference between the transconductor current and i_(π)is returned to the signal source, thereby generating a negativeresistance. A relationship between the current i_(π) and the conductanceassociated with this current (g_(π)) is given by g_(π)≡i_(π)/v_(in).Only the real parts of G_(m, eff) and g_(π) contribute to the equivalentnegative resistance. Therefore, R_(Eq) can be approximated as

$\begin{matrix}{R_{Eq} \approx \frac{- 2}{{{Re}\left\lbrack G_{m,{eff}} \right\rbrack} - {{Re}\left\lbrack {\mathcal{g}}_{\pi} \right\rbrack}}} & (2)\end{matrix}$Equation (2) suggests that R_(Eq) degrades rapidly as Re[g_(π)]approaches Re[G_(m, eff)] and has a distinct corner frequency which willbe revisited next using simulations. An expression for thenegative-to-positive transition frequency of R_(Eq)(ω_(tran)) can becalculated by considering the condition Re[G_(m, eff)]−Re[g_(π)]≦0,which results in

$\begin{matrix}{\omega_{tran} = {\sqrt{\frac{\left( {1 + \frac{r_{b}}{r_{\pi}}} \right)\left( {{\mathcal{g}}_{m} - \frac{1}{r_{\pi}}} \right)}{r_{b}C_{\pi}^{2}}}.}} & (3)\end{matrix}$Assuming r_(b)/r_(π)<<1, r_(π)=β/g_(m), and β>>1 where β is thebase-to-collector current gain, then equation (3) can be simplified to

$\begin{matrix}{\omega_{tran} \approx \sqrt{\frac{\omega_{T}}{r_{b}C_{\pi}}}} & (4)\end{matrix}$where ω_(T)=g_(m)/C_(π). For the MOS version of the cross-coupledstructure, r_(b) and C_(π) are replaced with r_(g) and C_(gS). Equation(4) shows that the transition frequency is a strong function of the biascurrent, device size, and base resistance. In the case of the MOStransistor, a multiple-finger layout may be used to drastically minimizegate resistance. On the other hand, in the case of the BJT transistor,the relatively high base resistance of the BJT in comparison to the gateresistance of the CMOS device can result in a lower transitionfrequency, despite its higher ω_(t). FIG. 3A shows the simulated R_(Eq)and C_(Eq) for the BJT and MOS cross-coupled cells using the 0.25-μmBiCMOS and 0.18-μm CMOS technologies, respectively, at a bias current of2 mA. It can be seen that the BJT-based design shows a smaller |R_(Eq)|than its CMOS counterpart at low frequencies due to its highertransconductance value. However, it has a much lower transitionfrequency (˜28 GHz) as compared to the CMOS case (˜53 GHz). FIG. 3Bshows plots for |R_(Eq)| for the BJT and MOS cross-coupled structuresusing equation (2). It can be seen that equation (2) predicts the rapiddegradation of |R_(Eq)| after a certain corner frequency. Increasing thebias current increases ω_(t) and hence increases the transitionfrequency. This implies that a low base (gate) resistance design isdesirable not only from a noise performance perspective but also from alow-power implementation perspective. This analysis suggests that acareful layout is desirable to increase the transition frequencyespecially for the CMOS case where the gate resistance can be reducedsubstantially by appropriate layout techniques without any seriousimpact on ω_(t) and/or C_(gs).

2) Buffer Stage Design

Another factor that impacts the maximum attainable frequency ofoscillation is the buffer stage. Buffer stages are usually implementedas emitter followers because of their high input impedance and widebandwidth. FIG. 4 shows the simplified circuit schematic for the VCOcore coupled to a buffer. The input admittance Y_(BI) of the bufferstage can be written as

$\begin{matrix}{Y_{BI} = {\frac{1}{Z_{L}\left\lbrack {1 + {\frac{r_{\pi}}{1 + {{j\omega}\; C_{\pi}r_{\pi}}}\left( {{\mathcal{g}}_{m} + \frac{1}{Z_{L}}} \right)}} \right\rbrack}.}} & (5)\end{matrix}$When the load impedance is resistive, Z_(L)=R_(S), the effective inputshunt resistance and capacitance looking into the buffer are given by

$\begin{matrix}\begin{matrix}{R_{{Eq},{BI}} = {R_{S}\frac{\left\lbrack {1 + {\beta\left( {1 + \frac{1}{{\mathcal{g}}_{m}R_{S}}} \right)}} \right\rbrack^{2} + \left( {\beta\frac{\omega}{\omega_{T}}} \right)^{2}}{1 + {\beta\left( {1 + \frac{1}{{\mathcal{g}}_{m}R_{S}}} \right)} + \left( {\beta\frac{\omega}{\omega_{T}}} \right)^{2}}}} \\{\approx {R_{S}\left\lbrack {1 + {\left( \frac{\omega_{T}}{\omega} \right)^{2}\left( {1 + \frac{1}{{\mathcal{g}}_{m}R_{S}}} \right)^{2}}} \right\rbrack}}\end{matrix} & (6) \\\begin{matrix}{C_{{Eq},{BI}} = {C_{\pi}\frac{r_{\pi}^{2}\left( {\frac{{\mathcal{g}}_{m}}{R_{S}} + \frac{1}{R_{S}^{2}}} \right)}{\left\lbrack {1 + {r_{\pi}\left( {{\mathcal{g}}_{m} + \frac{1}{R_{S}}} \right)}} \right\rbrack^{2} + \left( {\omega\; C_{\pi}r_{\pi}} \right)^{2}}}} \\{\approx {\frac{1}{\omega_{T}R_{S}}{\frac{\left( {1 + \frac{1}{{\mathcal{g}}_{m}R_{S}}} \right)}{\left( {1 + \frac{1}{{\mathcal{g}}_{m}R_{S}}} \right)^{2} + \left( \frac{\omega}{\omega_{T}} \right)^{2}}.}}}\end{matrix} & (7)\end{matrix}$If it is assumed that β>>1 and ω−ω_(T), then the approximations shown inequations (6) and (7) may be made. It is desirable that R_(Eq, BI) islarge enough so as not to reduce the loaded Q of the tank, whileC_(Eq, BI) is small enough not to limit the frequency tuning range. Inmany integrated transceiver designs, the buffer drives an internalcapacitive load C_(L), in which case the effective shunt resistance andcapacitance looking into the buffer input are now as follows:

$\begin{matrix}{R_{{Eq},{BI}} = {- \frac{\left( {1 + {{\mathcal{g}}_{m}r_{\pi}}} \right)^{2} + {\omega^{2}{r_{\pi}^{2}\left( {C_{\pi} + C_{L}} \right)}^{2}}}{\omega^{2}r_{\pi}{C_{L}\left( {{{\mathcal{g}}_{m}r_{\pi}C_{\pi}} - C_{L}} \right)}}}} & (8) \\{C_{{Eq},{BI}} = {\frac{{\left( {1 + {{\mathcal{g}}_{m}r_{\pi}}} \right)C_{L}} + {\omega^{2}r_{\pi}^{2}C_{\pi}{C_{L}\left( {C_{\pi} + C_{L}} \right)}}}{\left( {1 + {{\mathcal{g}}_{m}r_{\pi}}} \right)^{2} + {\omega^{2}{r_{\pi}^{2}\left( {C_{\pi} + C_{L}} \right)}^{2}}}.}} & (9)\end{matrix}$Equation (8) predicts a negative input resistance at the buffer inputwhen g_(m) r_(π)>C_(L)/C_(π). This condition is easily met as g_(m)r_(π)(=β) can easily be greater than ten. This additional negativeresistance provided by the buffer can be utilized by the VCO core whendriving a capacitive load. FIG. 5 shows the small-signal model for theVCO core and buffer load. The combined negative resistance is equal to(R_(Eq)∥2 R_(Eq, BI)). The negative resistance provided by the bufferreduces the g_(m) requirement of the cross-coupled cell and hence can beused to reduce power consumption and noise. Equation (9) predicts thatthe effective shunt capacitance is smaller than C_(π) or C_(L), whichallows for high-frequency design and wider tuning range. This basicnegative resistance seen in the buffer due to capacitive emitterdegeneration may be used to build a novel negative resistance cell forthe VCO as described in the following sections.

The impedance looking at the output of the buffer Z_(BO) determines thebandwidth of the buffer. In a normal common base amplifierconfiguration, the output impedance is equal to ˜1/g_(m, buffer) at lowfrequencies. However, when driven by a high-impedance oscillator,Y_(OSC) affects Z_(BO) as shown in FIG. 4. The output impedance for thisconfiguration is given by

$\begin{matrix}{Z_{BO} = \frac{Z_{\pi} + Z_{OSC}}{{{\mathcal{g}}_{m,{buffer}}Z_{\pi}} + 1}} & (10)\end{matrix}$where Z_(π)=(1/s C_(π)∥r_(π)and Z) _(OSC)=1/Y_(OSC). FIGS. 6A and 6Bshow circuit and bias details for MOS (FIG. 6A) and bipolar (FIG. 6B)oscillator cores. The oscillator admittance Y_(OSC) is a strong functionof Z_(biasL) and Z_(biasC) as well as Y_(BI). Nevertheless, because thereal part of Z_(BO) tends to increase with an increasing base impedance,an optimistic pole frequency produced at the emitter of the buffer stagecan be derived and given by

$\begin{matrix}{\omega_{Pole} = \frac{{\mathcal{g}}_{m,{buffer}}}{C_{L}}} & (11)\end{matrix}$This pole frequency has to be higher than the oscillation frequency toprevent output signal attenuation. More importantly, the signal suffersfairly large phase shift around the pole frequency, and relatively smallprocess variations can introduce large relative phase shift between twooutput signals when the pole frequency is close to the oscillationfrequency. FIG. 7 is a plot of the pole frequency ω_(Pole) as a functionof the load capacitance C_(L) at the output of the buffer stage forbipolar and MOS implementations at a 1-mA bias current. The MOS designhas a lower pole frequency even with a relatively small load capacitancedue to its lower g_(m). This implies that, even though the MOScross-coupled cell can provide a negative resistance up to very highfrequencies, the smaller bandwidth of the buffer stage can limit thepractical maximum attainable oscillation frequency.

3) Parasitic Capacitance and Tuning Range

Another factor that determines the maximum attainable oscillationfrequency for a given technology and power budget are the parasiticcapacitances of the various components. The maximum oscillationfrequency of the circuit in FIG. 1 is 1/√{square root over(L(C_(Fix)+C_(Eq)))}. When a desired tuning range Δω is required, themaximum attainable center frequency can be described as

$\begin{matrix}{\omega_{Max} = \frac{1}{\left( {1 + \frac{Tune}{200}} \right)\sqrt{L_{Min}\left( {C_{Fix} + C_{Eq}} \right)}}} & (12)\end{matrix}$where Tune is the tuning range as a percentage of the center frequency,L_(Min), is the smallest feasible inductance without suffering severeprocess variations, C_(Ex) is the fixed sum of parasitic capacitancescontributed by the varactor, the inductor, and the buffer, and C_(Eq) isthe effective shunt capacitance of the negative resistance cell. Theeffective capacitance of the cross-coupled cell is ˜C_(π)/2. At highfrequencies, this along with the effective capacitance from the bufferstage may become a significant portion of the overall capacitance andlimit the maximum attainable oscillation frequency and tuning range.

This subsection showed the mechanisms that degrade the R_(Eq) generatedby the cross-coupled cell and showed how the effective capacitance fromthe buffer and negative resistance cell limits the maximum attainablefrequency and tuning range. These limitations have motivated a newnegative resistance cell, described in the next subsection, that has ahigher negative to positive transition frequency and lower effectivecapacitance, thereby enabling low-power low-noise high-frequency design.While the embodiments are technology-independent, certain benefits arerealized in BiCMOS embodiments, and hence the following sections willfocus on a BiCMOS design.

B. Novel Negative Resistance Cell Design

As seen in the previous section, a capacitive emitter degeneratedtransistor can generate a negative resistance. FIG. 8 shows asingle-ended negative resistance cell using capacitive emitterdegeneration. The R_(Eq) and C_(Eq) can be described using the formulasin (8) and (9). When a voltage is applied to the base, part of itappears across C_(π), which in turn generates the transconductorcurrent. Part of this transconductor current is returned to the signalsource itself via the capacitor-capacitor divider. A portion of thisreturning current has a 180 phase shift from the applied voltage andthis results in a negative resistance. This negative resistance cell hasa very small effective capacitance. First, C_(π) and C_(e) are inseries. Second, the g_(m) cell affects the charge buildup across eachcapacitor and increases the effective C_(π) while decreasing theeffective C_(e), thus further reducing the effective series capacitance.This cell also has a high R_(Eq) transition frequency. The smalleffective capacitance has a higher impedance than C_(π), resulting in asmaller effective r_(g). This causes the voltage drop across r_(g) andthe phase shift from the base voltage to the voltage across C_(π) to besmaller than in the cross-coupled cell. So, it retards the degradationmechanism and increases the transition frequency. However, emitterdegeneration decreases the effective transconductance. Because theR_(Eq) transition frequency is also a function of g_(m), the reducedeffective transconductance limits the improvement in the R_(Eq)transition frequency and increases the |R_(Eq)| value. The increased|R_(Eq)| typically requires a higher Q tank design and hence higher Qinductor design which is nontrivial at high frequencies.

A novel capacitive emitter-degenerated negative resistance cell thatmitigates the reduction in issue mentioned above will now be discussed.FIG. 9 illustrates a novel negative resistance cell 900. In someembodiments, two capacitive emitter-degenerated negative resistancecells Q1 and Q2 are interconnected by using a cross-coupled NMOS pair M1and M2. The gate and drain of each NMOS device is connected to theemitters of each negative resistance cell, respectively. Thecross-coupled NMOS pair M1 and M2 works both as emitter-degeneratingcapacitors and provides additional transconductance to improve thenegative resistance value. FIG. 10 shows the equivalent small-signalcircuit model for the novel negative resistance cell. The inputadmittance can be calculated as

$\begin{matrix}{Y_{IN} = \frac{\frac{1}{2}\left\lbrack {{{\mathcal{g}}_{m\; 2}\left( {\frac{r_{\mathcal{g}}}{Z_{\mathcal{g}}} - 1} \right)} + \frac{1}{Z_{\mathcal{g}}}} \right\rbrack}{\left\lbrack {1 + {{\mathcal{g}}_{m\; 1}Z_{\pi}^{\prime}}} \right\rbrack + {Z_{\pi}\left\lbrack {{{\mathcal{g}}_{m\; 2}\left( {\frac{r_{\mathcal{g}}}{Z_{\mathcal{g}}} - 1} \right)} + \frac{1}{Z_{\mathcal{g}}}} \right\rbrack}}} & (13)\end{matrix}$where Z′_(π)=(r_(π)∥1/sC_(π)),Z_(π)=r_(b)+Z′_(π), Z_(g)=r_(g)+1/sC_(gs),and g_(m1) and g_(m2) are transconductances of the BJT and the nMOStransistor, respectively. If r_(b) and r_(g) are ignored, the equivalentshunt resistance is given by

$\begin{matrix}{R_{Eq} = \frac{- {2\left\lbrack {\left( {\frac{1}{r_{\pi}} + {\Delta\;{\mathcal{g}}}} \right)^{2} + \left( {\omega\; C_{T}} \right)^{2}} \right\rbrack}}{{\left( {\frac{1}{r_{\pi}} + {\Delta\;{\mathcal{g}}}} \right)\left( {\frac{{\mathcal{g}}_{m\; 2}}{r_{\pi}} + {\omega^{2}C_{gs}C_{\pi}}} \right)} - {\omega^{2}{C_{T}\left( {\frac{C_{gs}}{r_{\pi}} - {C_{\pi}{\mathcal{g}}_{m\; 2}}} \right)}}}} & (14)\end{matrix}$where Δg_(m)=g_(m1)−g_(m2) and C_(T)=C_(π)−C_(gs). For a fixed biascurrent, the g_(m) of the BJT is to first-order insensitive to devicegeometry, but the g_(m) of MOS device increases as the square root ofthe device size. To find an optimum g_(m1)/g_(m2) ratio, letg_(m1)=δg_(m2), and g_(m2)=K√{square root over (C_(gs))}, where K is aconstant. Using this relationship and assuming that g_(m1)r_(π)>>1, thenequation (14) can be simplified to:

$\begin{matrix}{R_{Eq} = \frac{- {\frac{2}{\delta}\left\lbrack {\left( {1 - \delta} \right)^{2} + {\left( \frac{\omega}{\omega_{T}} \right)^{2}\left( {1 + \frac{\Gamma^{2}}{C_{\pi}}} \right)}} \right\rbrack}}{{\left( {1 - \delta} \right){{\mathcal{g}}_{m\; 1}\left( {\frac{1}{\beta} + \frac{\omega^{2}\Gamma}{\omega_{T}K}} \right)}} - {{\omega^{2}\left( {\frac{\Gamma}{\beta\; K} - \frac{1}{\omega_{T}}} \right)}\left( {C_{\pi} + \Gamma^{2}} \right)}}} & (15)\end{matrix}$where ω_(T)=g_(m1)/C_(π) and Γ=Δg_(m1)/K

FIG. 11 is a plot of the expression in equation (15) as a function of δfor different values of g_(m1). This shows that the R_(Eq) is optimizedwhen δ is near unity, i.e., g_(m1)≈g_(m2). Additionally, it shows thatthis ratio is more critical than the magnitude of g_(m1) itself. Forexample, a 15-mA/V-15-mA/V combination results in a better R_(Eq) than a30-mA/V-15-mA/V combination.

FIGS. 12 and 13 show the simulated R_(Eq) and C_(Eq) results for thecross-coupled cell, the simple capacitively degenerated cell, and thenovel cell 900, respectively. All designs use a 2-mA bias current anduse the same BJT size. As shown in FIGS. 12 and 13, the simplecapacitive degeneration cell shows a higher R_(Eq) transition frequencybut a larger |R_(Eq)| in comparison to the cross-coupled cell. The novelcell 900 also has a higher transition frequency in comparison to thecross-coupled cell, but it shows a better R_(Eq) in comparison to thesimple capacitively degenerated cell. This implies that the novel cell900 may be particularly useful for low-power low-noise design forfrequencies above the transition frequency of the cross-coupled cell.This is because it does not generally require an increased bias currentfor a proportional increased g_(m), which would also increase the noisefrom the transistor. FIG. 13 shows that the novel cell 900 has aslightly higher C_(Eq) in comparison with the simple capacitivelydegenerated cell between 20-40GHz, but this value is much smaller thanthe value of C_(Eq) of the cross-coupled cell. Additionally, in someembodiments the novel cell 900 shows an inductive impedance at lowfrequencies as shown in FIG. 13. This simulated inductance using anactive device and capacitor has a lower Q in comparison with a passiveinductor and, due to its large inductance value, it has minimal effecton the oscillator operation even if the tank is tuned within thatfrequency range. However, it shows that it is possible to build aparasitic capacitance free negative resistance cell.

The analysis results in FIG. 11 suggest that a BJT-BJT combinationinstead of a BJT-MOS combination may be preferred for better g_(m)matching for the novel cell. However, even though a BJT-BJT combinationmay result in a better R_(Eq), the relatively high r_(b) of the BJTtypically results in a low transition frequency, and its benefit reducesto the small effective capacitance only.

C. Common-Mode and Differential-Mode Oscillation

One distinct difference between the capacitively degenerated cell andthe cross-coupled cell is its common-mode behavior. The common-modeinput admittance for the ideal cross-coupled cell in FIG. 2 is near zero(Y_(in)≈0). FIG. 14 shows the common-mode equivalent circuit schematicfor the capacitively degenerated cell. Unlike the cross-coupled cell,each half circuit of the capacitively emitter degenerated cell providesnegative resistance. However, for common-mode signals, the emitterdegeneration capacitor connected between two emitters in series (C_(S))does not have any effect on the common-mode impedance. Only thecapacitors connected to the ground act as a degeneration capacitor.Therefore, when C_(S)=0, each half of the circuit has the same effectiveresistance and capacitance as in the differential mode, i.e.,R_(EqD)=R_(EqC) and C_(EqD)=C_(EqC). In this case, the differential- andcommon-mode admittances can be described as

$\quad\begin{matrix}{{R_{EqH} = {R_{EqC} = R_{EqD}}}{C_{EqH} = {C_{EqC} = C_{EqD}}}{Y_{{IN},C} = {\frac{2}{R_{EqH}} + {{j\omega 2}\; C_{EqH}}}}{Y_{{IN},D} = {\frac{1}{2R_{EqH}} + {{j\omega}{\frac{C_{EqH}}{2}.}}}}} & (16)\end{matrix}$The equations predict that the common-mode |R_(Eq)| is four timessmaller than the differential-mode |R_(Eq)|, and common-mode C_(Eq) isfour times larger than the differential-mode C_(Eq). This implies thatthe capacitive emitter degeneration cell is more prone to oscillate incommon-mode when C_(S)=0.

FIG. 15 shows the simulated common-mode and differential-mode R_(Eq) fora capacitively emitter-degenerated cell where C_(S)=0. As seen in FIG.15, the common mode shows a much smaller |R_(Eq)|. When this type ofnegative resistance cell is used, it is desirable to design the tankbias network to prevent common-mode oscillation. FIG. 16 shows the LCtank with a center tapped inductor and capacitor including the biasnetwork. If Z_(biasL) and Z_(biasC) are very small, the common-modeimpedance to ground becomes (L/2∥2C), and the circuit can now oscillateat ω=1/√{square root over (L(C+C_(EqH)))} in the common mode. In fact,when Z_(biasL) and Z_(biasC) are zero, each half circuit becomes anindependent oscillator, and there is no phase relationship constraintbetween two output signals. If Z_(biasL) and Z_(biasC) are very large,the common-mode impedance of the tank becomes very large, and thecircuit cannot oscillate in the common mode. If the bias networkimpedance is zero, the circuit prefers to oscillate in the common mode.Thus, a large bias network impedance converts the oscillation mode fromthe common to differential mode. FIG. 17 shows the oscillation modeconversion from common mode to differential mode for the same circuit bysimply altering the bias network impedance. The differential-mode signalis shifted down on this plot for graphical convenience only.

In the novel negative resistance cell with the cross-coupled MOS pair,the common-mode admittance of the MOS pair is near zero. Only theeffective input capacitance of the buffer contributes to the common-modenegative resistance. This makes the novel cell less susceptible tocommon-mode oscillations as compared to a simple capacitivelyemitter-degenerated cell.

D. Wide Tuning Range

A wide tuning range is often important because it can accommodate moreprocess and temperature variations. For high-frequency oscillatordesign, the effective capacitance from the negative resistance cell isone of the key factors that limit a wide tuning range. The novelcapacitive emitter degenerating cell has a small effective capacitance.FIGS. 18A and 18B graphically show the mechanism that results in a smalleffective capacitance. In FIGS. 18A and 18B, Q3 and Q4 are buffertransistors. In the cross-coupled structure illustrated in FIG. 18A, thetank looks into the base of Q2, the collector of Q1, and the base ofbuffer transistor Q3. However, in the novel topology 1800 illustrated inFIG. 18B, the tank only looks into the base of Q1. Furthermore, theequivalent capacitance looking into the base of is much smaller than theC_(π) of Q1, as shown above.

FIG. 19 shows how the effective capacitance of a negative resistancecell affects the oscillator tuning range. For this simulation, atwo-turn spiral inductor with 740-pH inductance with 17-fF parasiticcapacitance and diode varactors with capacitance range from 28.6 to 68.4fF are used. The tuning range and center frequency go down rapidly withincreasing parasitic capacitance of the negative resistance cell. Inparticular, if the center frequency is kept constant by changing thevaractor size, the tuning range reduces even more rapidly, as shown inFIG. 19. For example, if the load at the output port in FIG. 18 is 200fF, the equivalent shunt capacitance looking into the base of Q3 isapproximately 44.4 fF. This parasitic loading causes severe frequencyand tuning range limitations for the cross-coupled topology, as can beseen in FIG. 19. However, in the novel topology disclosed herein, theequivalent shunt capacitance looking into the base of Q3 functions aspart of the emitter-degenerating capacitance, and the effectiveparasitic capacitance loading the tank is further attenuated by Q1.

A small effective capacitance also provides more room to increase theinductor size in the tank. In many cases, the R_(p) of LC tank increaseswith increasing inductance value, so a large inductance enables largeoutput signal power. Depending on the technology and the designconstraint, the Q of the inductor can increase with increasinginductance. In this case, both the increased signal power and improved Qcontributed by the small effective capacitance can result in lower phasenoise, as can be seen in the modified Leeson's phase noise formula,described in J. W. M. Rogers, J. A. Macedo, and C. Plett, “The effect ofvaractor nonlinearity on the phase noise of completely integrated VCOs,”IEEE J. Solid-State Circuits, vol. 35, pp. 1360-1367, September 2000 andshown as follows:

$\begin{matrix}{{L\left( {{\Delta\; f},K_{VCO}} \right)} = {10\mspace{11mu}\log\left\{ {{\left( \frac{f_{0}}{2Q\;\Delta\; f} \right)^{2}\left\lbrack {\frac{FkT}{2P_{0}}\left( {1 + \frac{f_{C}}{\Delta\; f}} \right)} \right\rbrack} + {\frac{1}{2}\left( \frac{K_{VCO}\upsilon_{m}}{2\Delta\; f} \right)^{2}}} \right\}\mspace{11mu}\left( 1 \right.}} & (17)\end{matrix}$where

-   -   L(Δf, K_(VCO)) phase noise in dBc/Hz;    -   f₀ frequency of oscillation in Hz;    -   Δf frequency offset from the carrier in Hz;    -   F noise figure of the transistor amplifier;    -   k Boltzmann's constant in J/K;    -   T temperature in K;    -   P₀ RF power produced by the oscillator in W;    -   f_(C) flicker noise corner frequency in Hz;    -   K_(VCO) gain of the VCO in Hz/V;    -   v_(m) total amplitude of all low-frequency noise sources in        V/√{square root over (Hz)}.        The first term within the log in equation (17) predicts a        decreased phase noise with increasing tank and signal power.        This discussion emphasizes that the small effective capacitance        of the negative resistance cell is not only advantageous for        high frequency and wide tuning design, but results in additional        flexibility during the LC tank phase noise optimization process.

II. Experimental Results of a Particular Embodiment

In one embodiment, a 20-GHz VCO as described above with a 5-GHz tuningrange has been designed using the IBM 0.25-m BiCMOS process. It isdesirable to take into account the g_(m1)/g_(m2) ratio for R_(Eq)optimization of various embodiments. The g_(m1)/g_(m2) (δ) ratio in someembodiments is about 0.3. At 20 GHz, the simulated R_(eq)≈−500Ω andC_(EQ t)≈13 fF. This includes the effect of the buffer. It should benoted that C_(Eq) is about 1/9th the C_(π) of Q1, which is equal to 126fF. In some embodiments, the VCO uses a two-stage emitter follower asbuffers for each output. The capacitive impedance looking into thisbuffer works as a degeneration capacitance and contributes to thenegative resistance. However, as described in the previous section, thedegeneration using active devices is more desirable and the buffer hasbeen designed to have minimal impact on this design. In someembodiments, two back-to-back junction diodes as described above areused as the varactor, and the anode is connected to the base of the BJTto minimize the N/substrate parasitic capacitance effect. The spiralinductor uses two turns to generate a 740-pH inductance. A singledifferential inductor is used for higher Q and to save area. This singleinductor design without a center tap used in some embodiments alsoprevents common-mode oscillation. A chip microphotograph and VCO layoutdetails according to an embodiment are shown in FIG. 20.

For the measurements, RF probes were used to directly connect to thebare die. A single-ended measurement setup has been used throughout.FIG. 21 shows the measured output power spectrum of the 20-GHzoscillation signal. The measured tuning range is compared with thesimulated tuning range in FIG. 22( a). Measurement results show morethan 5-GHz (25%) tuning range. This wide tuning was possible because ofthe low effective capacitance of the novel negative resistance cell.FIG. 22( b) shows simulated oscillation frequency at a fixed biascondition as a function of the temperature for different processcorners. For these corner simulations, only the process corner parameterfor bipolar devices has been considered, and six sigma variations havebeen considered. FIG. 22( b) shows that temperature and processvariation results in about 4-GHz variation of the center frequency,clearly showing the desirability of a wide tuning range design that cantolerate temperature and process variations. The VCO core of someembodiments consumes only 2 mA, and each emitter follower branch drains0.5 mA from a 4.5-V supply, respectively. This low bias current supportsthe low-power design capability of the novel topologies of theembodiments described above. Despite the wide tuning range, the maximumoutput power variation was less than 3.5 dBm over the whole frequencytuning range, as shown in FIG. 23.

A low-power signal close to the noise floor is injected at the oppositeside of differential output to remove the random drifting of the freerunning VCO, as shown in FIG. 24A. The phase noise of the injectedsignal was 121 dBc/Hz at a 2-MHz offset from the 19.4-GHz carrier. Athigh injection levels, the phase noise of the VCO follows the phasenoise of the injected signal source. However, at low injection powerlevels, the locking range reduces and the phase noise approaches itsintrinsic level, as shown in FIG. 24B.

FIG. 25 shows the measured injection locking range as a function ofinjected signal power and the measured phase noise at an injected signalpower of 58 dBm. At this injection level, the lock range is about 800kHz. The actual power delivered to the tank is much smaller because ofthe attenuation through the buffer stage. The phase noise is measured ata 2-MHz offset from 19.4 GHz to eliminate the phase-noise attenuationthrough injection locking. The measured phase noise was 105.5 dBc/Hz.This value is obtained using an NMOS noise coefficient (γ) of ⅔ and noinduced gate noise contribution. For short-channel devices, γ may reach2.5, and induced gate noise should be included, as simulationsunderestimate the actual phase noise. It should be noted that theresults detailed above are for a particular embodiment, and that otherembodiments may exhibit different results.

III. Conclusion

In the previous sections, factors affecting the design of a negativeresistance cell based LC VCOs have been discussed. The analysis includedparasitics from the VCO core and the buffer stage. This discussion alsoanalyzed the high-frequency performance and limitations of thecapacitively degenerated negative resistance cell. Based on theseanalyses, a novel negative resistance cell topology is described thatcan overcome the limitations of the existing topologies. In someembodiments, the novel cell uses a cross-coupled MOS pair as adegeneration cell. The cross-coupled MOS pair contributes additionalconductance and allows for the novel cell to have a higher maximumattainable oscillation frequency and better negative resistancecharacteristics in comparison with other topologies at high frequencies.These properties combined with its small effective capacitance enableslow-power low-noise high-frequency VCO implementations. One embodimentincludes a design for a 20-GHz fully integrated LC VCO implementation inthe IBM SiGe 0.25-m BiCMOS technology.

Various embodiments of the invention have been described. Thedescription of the exemplary embodiments of the invention is presentedfor the purposes of illustration and description, and is not intended tobe exhaustive or to limit the invention to the precise forms disclosed.Many modifications and variations are possible in light of the aboveteaching.

As an example, the invention further contemplates a method forgenerating signals using a VCO as described herein, and well as methodsfor manufacture of the disclosed VCO. In addition, the VCO designdescribed herein may be useful in a number of different applications,including wired and wireless communication systems. For example, a VCOas described herein may be implemented within a phase-locked loop (PLL)of a communication device.

The terminology used in this application is meant to include all ofthese environments. It is to be understood that the above description isintended to be illustrative, and not restrictive. Many other embodimentswill be apparent to those of skill in the art upon reviewing the abovedescription. Therefore, it is manifestly intended that the inventivesubject matter be limited only by the following claims and equivalentsthereof.

The Abstract is provided to comply with 37 C.F.R. § 1.72(b) to allow thereader to quickly ascertain the nature and gist of the technicaldisclosure. The Abstract is submitted with the understanding that itwill not be used to limit the scope of the claims.

1. A voltage controlled oscillator (VCO) comprising: aninductor-capacitor (LC) tank; and a negative resistance cell coupled tothe LC tank, wherein the negative resistance cell includes: a firstbipolar transistor, a second bipolar transistor, and at least twofield-effect transistors, wherein the first and second bipolartransistors are interconnected via the field-effect transistors. whereinthe LC tank is coupled to a base of the first bipolar transistor and toa base of the second bipolar transistor, the base of the first bipolartransistor and the base of the second bipolar transistor being the onlyconnections between the LC tank circuit and the negative resistancecell, and wherein the base of the first bipolar transistor is connectedto only the LC tank, and the base of the second bipolar transistor isconnected to only the LC tank.
 2. The VCO of claim 1, wherein an emitterof the first bipolar transistor is coupled to a gate of a first one ofthe field-effect transistors and an emitter of the second bipolartransistor is coupled to a gate of a second one of the field-effecttransistors.
 3. The VCO of claim 2, wherein the emitter of the firstbipolar transistor is coupled to a drain of the second one of thefield-effect: transistors and the emitter of the second bipolartransistor is coupled to a drain of a first one of the field-effecttransistors.
 4. The VCO of claim 3, wherein the negative resistance cellfurther comprises a current source that is coupled to a source of eachof the field-effect transistors.
 5. The VCO of claim 1, furthercomprising a buffer circuit for buffering an output of the VCO.
 6. TheVCO of claim 5, wherein the buffer circuit comprises: a first buffercoupled to the emitter of the first bipolar transistor, and a secondbuffer coupled to the emitter of the second bipolar transistor.
 7. TheVCO of claim 6, wherein the first and second buffer comprise emitterfollowers.
 8. The VCO of claim 1, wherein the field-effect transistorscomprise metal-oxide-semiconductor field-effect transistors (MOSFETs).9. The VCO of claim 1, wherein the field-effect transistors include NMOSdevices.
 10. The VCO of claim 1, wherein the negative resistance cellhas an input admittance calculated as:$Y_{IN} = \frac{\frac{1}{2}\left\lbrack {{g_{m\; 2}\left( {\frac{r_{g}}{Z_{g}} - 1} \right)} + \frac{1}{Z_{g}}} \right\rbrack}{\left\lbrack {1 + {g_{m\; 1}Z_{\pi}^{\prime}}} \right\rbrack + {Z_{\pi}\left\lbrack {{g_{m\; 2}\left( {\frac{r_{g}}{Z_{g}} - 1} \right)} + \frac{1}{Z_{g}}} \right\rbrack}}$where Z′_(π)=(r_(π)∥1/sC_(π)), Z_(π)=r_(b)+Z′_(π),Z_(g)=r_(g)+1/sC_(gs),and g_(m1) and g_(m2) are transconductance of the BJT and the nMOStransistor, respectively.
 11. A voltage controlled oscillator (VCO)comprising: a first pair of transistors including a first bipolartransistor and a second bipolar transistor; a second pair of transistorsincluding a first field-effect transistor and a second field effecttransistor, the first field effect transistor having a gate connected toa drain of the second field-effect transistor and to an emitter of thefirst bipolar transistor, the second field effect transistor having agate connected to a drain of the first field-effect transistor and to anemitter of the second bipolar transistor; a first buffer circuit coupledto the emitter of the first bipolar transistor, the first buffer circuitoperable to receive a low-power signal injection; a second buffercircuit coupled to the emitter of the second bipolar transistor, thesecond buffer circuit providing an output; and an inductor-capacitor(LC) tank directly connected to a base of the first bipolar transistorand directly connected to a base of the second bipolar transistor,wherein the base of the first bipolar transistor is connected to onlythe LC tank, the base of the second bipolar transistor is connected toonly the LC tank, and the base of the first bipolar transistor and thebase of the second bipolar transistor are the only connections to the LCtank.
 12. The VCO of claim 11, further comprising a current sourcecoupled to the second pair of transistors.
 13. The VCO of claim 11,wherein the VCO has a maximum operating frequency of at least 20 GHz.14. The VCO of claim 11, wherein the VCO has at least a 5 GHz tuningrange.
 15. The VCO of claim 11, wherein at 20 GHz the VCO has aneffective shunt capacitance (C_(Eq)) of approximately 13 femtofarads.16. The VCO of claim 11, wherein at 20 GHz the VCO has an effectivenegative resistance (R_(Eq)) of approximately −500 ohms.
 17. The VCO ofclaim 11, wherein the first buffer stage and the second buffer stageeach include a two-stage emitter follower.